The Integrated Circuit Exhibition of the 2026 China International Industry Fair (CIIF) recently took place at the National Exhibition and Convention Center in Shanghai. A national industry event for China’s integrated circuit sector, the exhibition brought together more than 300 companies working in advanced packaging, AI computing chips, advanced passive components, and other emerging fields. Launchip CEO Wang Daxiang was invited to deliver a keynote presentation titled “The Deep Integration of AI Processor Power Delivery Networks and Advanced Packaging.” During the event, he also unveiled the updated Silicon Capacitor Technology White Paper 2.0, sharing insights into the technical requirements, implementation approaches, R&D progress, and commercialization of domestically developed silicon-based passive devices in the era of high-performance AI computing.

Vertical Power Delivery for AI Chips Is a System-Level Engineering Challenge

　　According to Launchip CEO Wang Daxiang, the explosive growth of AI computing is pushing chip power delivery toward its physical limits. Leading AI chips now consume power at the kilowatt level, while operating voltages continue to fall. NVIDIA’s operating voltages, for example, have declined from 1.30–1.35 V in the 2006 Tesla generation to 0.65–0.80 V in the Blackwell generation from 2025 onward. The combination of high current and tight voltage margins presents three challenges for power delivery networks (PDNs):

• 　　Resistive voltage drop: At high currents, even very small resistance can cause significant voltage loss.

• 　　Transient voltage fluctuations: Rapid changes in load current, combined with parasitic inductance, can produce severe voltage fluctuations.

• 　　Capacitor discharge voltage drop: Before the voltage regulator can respond, decoupling capacitors must provide immediate power, requiring sufficient capacitance.

　　As conventional lateral power delivery architectures approach their performance limits, the industry is increasingly moving toward vertical power delivery across multiple levels, including PCBs, substrates, and 2.5D/3D integration.

　　For kilowatt-class AI chips, power delivery is no longer an isolated board-level design task. It is a system-level engineering challenge involving tightly coupled chips, substrates, advanced packaging, and passive devices. With ultra-low equivalent series resistance and inductance (ESR/ESL), high capacitance density, and an ultra-thin profile suitable for co-packaging, 3D silicon capacitors based on deep-trench capacitor (DTC) technology have become a core solution for near-die decoupling. They are also increasingly being used as flying capacitors in integrated voltage regulators (IVRs). Meanwhile, on-chip magnetic-core inductors are a critical building block for 2.5D/3D IVRs. Together, these devices support the implementation of next-generation vertical power delivery networks for AI chips.

　　Vertical power delivery for AI chips is one of the most complex challenges in the history of chip engineering. It involves backside power delivery, coupled thermal, electrical, mechanical, and magnetic effects across multiple scales in advanced packaging, associated simulation challenges, and the process compatibility of magnetic materials. Addressing these challenges requires open collaboration and joint development across the industry. Launchip will continue to increase its investment in silicon-based passive device R&D, accelerating the development and commercialization of substrate-embedded capacitors, DTCs integrated into silicon interposers, and on-chip magnetic-core inductors. The company will also continue to expand shared technical resources, including its white papers, to support AI chip vertical power delivery networks built on advanced passive devices and packaging technologies.

Silicon Capacitor Technology White Paper 2.0 Officially Released

　　Unveiled at the event, Silicon Capacitor Technology White Paper 2.0 substantially expands and updates the first edition in five areas:

• 　　A comprehensive review of the evolution of silicon capacitor technology;

• 　　Additional measured data comparing silicon capacitors with multilayer ceramic capacitors (MLCCs);

• 　　New technical solutions, simulation models, and engineering case studies covering substrate-embedded capacitors, glass substrate integration, 2.5D silicon interposer integration, 3D integration, and other advanced packaging applications;

• 　　Broader component selection guidance for high-speed optical modules, power semiconductors, aerospace, medical electronics, and other applications;

• 　　Additional guidance on electrothermal simulation, reliability testing, process compatibility, and collaborative development across the supply chain.

　　The white paper provides chip design companies, packaging providers, substrate manufacturers, and system manufacturers with a comprehensive, reliable reference for component selection and development, supporting the adoption of domestically developed silicon capacitors at scale across the computing industry.

Multiple Silicon Capacitor Formats Address Vertical Power Delivery Requirements

　　Publicly available information shows that Launchip specializes in the design, development, and sale of silicon-based passive devices, including 3D silicon capacitors, silicon inductors, and silicon resistors. Its silicon capacitors combine high capacitance density, ultra-low ESL, and ultra-thin packaging for applications in AI computing, server power supplies, optical communications, and advanced packaging. With vertical power delivery as a key technology direction, the company is working to accelerate collaboration between silicon-based passive device developers and the advanced packaging supply chain.

　　Built on deep-trench capacitor technology, Launchip’s silicon capacitors offer a combination of small dimensions, low ESR, low ESL, high capacitance density, strong high-temperature and high-frequency performance, and no voltage bias effect. To address implementation requirements at different levels of vertical power delivery networks, Launchip has established two product lines ready for volume production: surface-mount silicon capacitors and substrate-embedded capacitors. The surface-mount products focus on very-high-frequency decoupling both inside and outside the package, while the embedded solutions enable high-density integration within package substrates. Both product lines have passed validation by multiple leading customers, offering domestically developed alternatives with internationally competitive key performance parameters.

　　The company is also progressing several R&D initiatives aligned with the longer-term evolution of advanced packaging. Capacitors embedded in substrate ABF layers are under joint development; silicon capacitor integration with glass substrates is included in its near-term roadmap; and a project to integrate DTCs into 2.5D silicon interposers has been formally initiated. Silicon capacitors are evolving beyond standalone surface-mount devices toward deeper integration with conventional substrates, glass substrates, and silicon interposers.

Magnetic-Core Inductors Address a Critical Gap in Domestic 2.5D/3D IVR Capabilities

　　Launchip has also made progress in inductor development. Its on-chip CZT (cobalt-zirconium-tantalum alloy) magnetic-core inductors are currently undergoing prototype fabrication and validation.

　　Magnetic-core inductors are the primary energy-storage components in DC step-down converters and are key components in 2.5D/3D IVRs and fully integrated voltage regulators (FIVRs). Their inductance density can be tens of times higher than that of air-core inductors. They also confine magnetic fields to reduce electromagnetic interference, making them one of the standard components in AI chip power delivery networks. Launchip’s on-chip magnetic-core inductors use a low-temperature redistribution layer (RDL) process compatible with CMOS fabrication, with an interleaved magnetic-core deposition structure designed to reduce eddy-current losses.

　　Domestic development of on-chip magnetic-core inductors remains largely at the laboratory research and patent-development stage. Launchip is calling for joint investment in process development and validation across the supply chain to address the gap in domestically developed passive devices for 2.5D/3D IVRs. Completing this “final piece of the puzzle” requires collaboration across equipment, processes, devices, chip design, and packaging.

From Standalone Devices to Device–Packaging–System Co-Development

　　Taking a platform-based approach, Launchip is expanding beyond individual components to build a comprehensive portfolio of silicon capacitors, silicon resistors, silicon inductors, and silicon interposers, while laying the groundwork for longer-term opportunities in IVRs. Built on a unified silicon semiconductor process platform, its portfolio provides one-stop coverage of power decoupling, high-frequency filtering, impedance matching, and integrated power management.

　　The company has secured dozens of core patents and offers more than 200 product models, with monthly production capacity exceeding 500 million units. It serves more than 20 customers at the validation or volume-production stage, has achieved volume deliveries for AI computing, high-performance servers, and high-speed optical modules, and has secured orders worth at least RMB 100 million.

　　In the era of advanced packaging and high-speed, high-performance chips, passive devices are evolving from standard components selected off the shelf into critical elements that must be considered early in chip and package definition. Launchip brings industry collaboration into the product definition stage, working closely with wafer fabs, packaging providers, and substrate manufacturers on joint process adaptation and reliability validation. By connecting device design, process development, and package integration, the company aims to address practical engineering challenges such as stress control and coupled electrothermal simulation, strengthening the foundations of the advanced chip ecosystem.